In such semiconductor circuits, information items stored in the storage capacitors of the memory cells are read out by activation of the bit lines and word lines. The electrical potential of two bit lines are detected by a signal amplifier in order to identify a storage state. The signal amplifier (sense amplifier) acts as voltage differential amplifier which, after the potential of an opened bit line has been read, amplifies this signal and writes it back to the opened memory cell. In the case of the folded bit line construction of integrated semiconductor memories, when reading from one of two adjacent bit lines, the reference potential used is that of the respective other bit line.
Each memory cell is read by activation of a word line and then of a bit line, as a result of which, in the case of a field-effect transistor as selection transistor, the inversion channel produces the electrical connection between the storage capacitor, for example, a trench capacitor, and the bit line. The word line serves as gate electrode in the region of the transistor. One of the source/drain regions is conductively connected to the trench capacitor; the other source/drain region is electrically connected by a bit line contact to the bit line assigned to this transistor. The gate electrode, together with the gate oxide and a protective insulation layer, usually a nitride layer forms a patterned gate layer stack, the sidewalls of which are electrically insulated toward the side by means of a spacer, i.e., an insulating sidewall covering. The bit line contacts, which electrically connect the bit lines located at a higher level to the source/drain regions of the selection transistors, are arranged between mutually adjacent word lines equipped with spacers. The contact structures or bit line contacts thus connect an upper plane of the bit lines to a lower plane of the doping regions of the selection transistors and pass through a central plane in which the word lines are arranged.
In present-day semiconductor circuits, in particular, memory circuits, disturbance effects which disadvantageously affect the electrical switching behavior occur on account of the close spatial arrangement of a wide variety of structures. One disturbance factor is the lateral insulation of the word lines with respect to the contact structures or bit line contacts. The insulation is formed by the thin sidewall coverings of the word lines, as a result of which parasitic capacitances are formed.
During the read-out of a memory cell, both the word line and the bit line at whose crossover point the selection transistor of the memory cell is situated are activated. In this case, the electrical charge accumulated in the storage capacitor flows via the selection transistor out of the cell or is distributed between the cell and the connected bit line through to the signal amplifier. As a result, the electrical potential which is then present at the corresponding bit line terminal of the signal amplifier is attenuated with respect to the electrical potential of the charge previously stored in the memory transistor. Nevertheless, a potential difference remains measurable in comparison with another, usually adjacent bit line which is short-circuited with none of the connected storage capacitors.
This parasitic capacitance thus gives rise to an additional potential contribution which is superposed on the electrical potential which is expected on account of the capacitor capacitance and the bit line capacitance at the signal amplifier input. At the other input of the signal amplifier a non-activated bit line is present, in the case of which a comparable parasitic capacitance does not occur. Consequently, in the signal amplifier, the parasitic capacitance of the activated bit line is superposed on the potential difference of the two bit lines which is actually to be measured.
Such parasitic effects are conventionally compensated for by higher operating voltages and correspondingly higher quantities of charge of an integrated semiconductor circuit. However, this increases the current consumption, the heat supply and the space requirement of the integrated semiconductor circuit per memory cell.